#Modelsim simulation steps how to#
#Modelsim simulation steps code#

#Modelsim simulation steps how to#

Learners are encouraged to learn how to compile, force the input values, simulate as these steps won't be repeated in the forthcoming tutorials. This is how the VHDLВ logic gate codesВ are written, compiled, and simulated. The above values of A, B, Y corresponds to the Truth Table of the OR Gate. The values of A, B, Y at corresponding time intervals are given below. Move the cursor throughout the waveform graph from 0ps to 500ps. Now that all the input combinations for A and B (00,01,10,11) are forced to the input signals. Similarly, the other four input combinations are given and their outputs are verified as shown below.ДЇrom the waveform graph, the output Y changes according to the given Inputs A and B. Now, we can see that for A=0, B=0, Y=0, which verifies with Truth Table of OR Gate. There is a yellow colour cursor on the waveform, move the cursor so that the corresponding inputs and outputs are shown. Click the run icon, we can see the waveforms on the graph for 100 ps. There is a Run icon in the toolbar near the timer as shown below. Step 9:В Now that the inputs are given, let's Run the simulation. Set the Value to 0 for A and similarly for B set the value 0 and click OK. A menu pops up from that choose вЂњForceвЂќ option. Step 7:В Now, let us simulate the circuit by giving the inputs. Step 6:В The waveform window opens with declared inputs and outputs on the right side of the window as shown below. Right Click on the entity name (OR_gate) and click Add Wave as shown below. Click Work Here,В we can see our entity name (OR_gate). Step 4:В Once you select Start Simulation, a dialog box opens, and there is a folder called вЂњWorkвЂќ. On the ToolBar, there is an option called вЂќSimulateвЂќ as shown below. Now that the compilation is successful.В Let'sВ simulate the designed circuit.

#Modelsim simulation steps code#

Step 3:В If you find a red mark or unsuccessful please check your code if it has errors. The files are compiled and we can see a green tick mark вЂњГјвЂќ and вЂњCompile of entity name. To understand the general structure of the VHDLВ code, please refer to the first tutorial. Now that we know the Truth Table, let's start scripting the VHDLВ code for OR Gate. If you want to know the basics like what is or gate and how it works, you can check out the link for our previous tutorial. The Boolean function and Truth Table of the OR gate areВ given below. Let us start designing the basic logic gates using VHDL. Double click the OR_gate.vhd, an editor will open up on the right side of the window. Step 7:В Now that the file is added, we can start scripting our first VHDLВ program. Step 6:В The project will be created and the file OR_gateВ will be added as shown below. Here, for example, the file name is given as OR_gate. Give a file name and choose the file type as VHDLВ and click OK. Step 5:В ' Create a new project file' opens up. Step 4:В The project will be created and the вЂњAdd Items to the projectвЂќВ dialog box opens. For example, the project name given below is вЂњbasic_ logicgatesвЂќ Enter the name for your project and click OK as shown below. Step 3:В The create new project dialog box opens up.